The overall capacities of broadband satellites are increasing exponentially, and such capacity increases present unique challenges in the associated ground system and network designs. The goal of the system designers, system operators, and service providers is to support and provide efficient, robust, reliable and flexible services, in a shared bandwidth network environment, utilizing such high capacity satellite systems. Accordingly, current systems fail to adequately support efficient, robust, reliable and flexible broadband services, in such shared bandwidth network environments, in relation to demodulation of data streams with high symbol rates in high capacity satellite systems.
Examples of demodulation in satellite communications systems are described in U.S. Pat. No. 6,985,523 to Sims et al., titled “Method and System for Adaptive Equalization for Receivers in a Wide-Band Satellite Communications System,” and in U.S. Patent Application Publication No. 2002/0131528 to Clewer et al., titled “System and Method of Parallel Partitioning a Satellite Communications Modem,” the entireties of which are incorporated herein by reference. Further an example of automatic gain control and demodulation in satellite communications systems is described in U.S. Pat. No. 6,904,273 to Steber et al., titled “Method and System for Automatic Gain Control in a Satellite Communications System,” the entirety of which is incorporated herein by reference. However, known systems, such as those disclosed in U.S. Patent Application Publication No. 2002/0131528, were directed to burst, or bursty, modes of data transmission, and, as such, were not specifically directed to dealing with data streams with high symbol rates for symbol timing recovery in a continuous mode of transmission.
However, when a burst modem is used for signal processing, there is typically not a significant degree of continuity between a first burst to the next burst, etc. from burst to burst. Therefore, where signals are received and processed in a continuous mode problems to be address are typically different from those addressed in a discrete burst mode of signal transmission, as well as differences are typically present in the underlying the parallelization are different in the continuous burst mode.
Therefore, to parallelize the functions of a demodulator to process continuous bursts, i.e. particularly for continuous mode data transmission, as opposed to intermittent, or bursty, data transmission in the burst mode of data transmission, typically requires a different solution from that in processing discrete bursts, so that the signal processing modules are different for continuous mode processing than in the burst mode processing. Also, the carrier recovery loop for processing data received in a burst mode from that received in a continuous mode is likewise typically different, such as related to the carrier recovery function. While the equalizer function is a burst mode and in the continuous mode can be similar, the functions in the continuous mode are typically more complex than in the burst mode, and the symbol timing recovery is also likely different.
Also, while a parallel finite impulse response (FIR) implementation is known in relation to DVB-S2 demodulation, deficiencies can be present as to the symbol timing interpolation and carrier recovery for demodulation. For example, one significant drawback in current designs of a wide-band DVB-S2 modem for processing data streams with high symbol rates for symbol timing recovery is that the maximum clock speeds for processing data are limited by the maximum clock speeds of known application specific integrated circuits (ASICs) for implementing DVB-S2 type demodulation. Also, parallel designs for feed-forward linear systems, such as FIR filters, are known, but problems still are present as to processing high data rate streams for symbol timing recovery.
Receivers require that signals be sampled at the rate of at least twice the symbol-rate. This typically requires that all front-end signal processing be performed at least at twice the symbol-rate, including that for the symbol timing recovery loop. In a traditional modem this requirement typically forces the processing clock frequency to be at least twice the maximum symbol-rate being processed. But, for high throughput systems that deploy high symbol-rates, such processing requirement places a difficult design constraint on the modem forcing it to use a high frequency processing clock. The high frequency processing clock adds tighter timing constraints on the physical design of the modem and, thus, makes it more expensive to design and manufacture.
While use of a parallel architecture can assist with high frequency processing, such as by processing N samples in parallel in each clock, theoretically it can be possible to achieve the such processing throughput by using a clock that is N times slower than the one used for the traditional serial design. However, symbol timing recovery loops use the temporal dependency between neighboring samples to process information and determine the ideal sampling point. And parallel designs have a drawback in that they break the temporal dependency between neighboring samples.
In this regard, a known approach to processing data streams with high symbol rates for symbol timing recovery is to utilize two narrow band demodulators, such as by attaching or channel bonding them together multiplex them. However such combination of two narrow band filters has significant drawbacks in that processing is not done as a single wideband filter. Another significant drawback is that combining the two narrow band filters in effect utilizes two narrow-band demodulators. As such, efficient and effective use of the channel or spectrum of the channel typically is degraded, particularly with respect to use of bandwidth capacity, bandwidth capacity being a commercially important consideration, as to cost considerations.
Achieving efficient, robust, flexible and fast broadband services, in such a high capacity, shared bandwidth, satellite system network, as to demodulation of data streams with high symbol rates, however, poses unique challenges to system designers and operators. For instance, receivers of data streams require the signals to be sampled at the rate of at least twice the symbol-rate. This typically requires that all front-end signal processing be performed at twice the symbol-rate (in-phase quadrature (I/Q) imbalance correction, gain correction, decimation, symbol timing recovery, and channel-equalization). In addition, the DVB-S2 carrier-recovery for pilot-on mode typically requires that the data segment be buffered and the certificate revocation list (CRL) runs at least once backward and once forward and combine the phase estimates from the two runs. In order to maintain adequate throughput, this also typically requires that the CRL be processed at least twice as fast as the symbol-rate. For high data-rate systems with high symbol-rates, such as in satellite communications systems, this typically requires a very fast clock. For example, a maximum symbol-rate of 225 Msps, for example, would require a modem processing clock of at least 450 MHz. Such a high clock speed would not be desirable in that it would impose severe timing constraints on any modem ASIC design for demodulation.
What is needed is a system design that employs a dynamic and flexible architecture and methods for demodulation of high data-rate streams with high symbol-rates, such as satellite communications systems, or for high capacity computer network systems, that reduces the speed requirement of the clock to be slightly greater than the symbol-rate instead of twice the symbol-rate. What is further needed is a parallel design for the symbol timing recovery loop that preserves the temporal dependency between neighboring samples.
What is also needed is architecture and methods for DVB-S2 type demodulators to process high data-rate streams with high symbol-rates, with samples coming in at a much faster rate than the system clock is able to run. Therefore, what is further needed is architecture and methods for DVB-S2 type demodulators that are capable of receiving and processing DVB-S2 streams with high symbol-rates at or below the clock-rate of a modem.
What is additionally needed is architecture and methods that substantially ease the timing constraints on ASIC design for demodulation, and provide for adequate throughput for such data streams, as well as would meet various requirements and desires associated with efficient, robust, reliable and flexible broadband services in a high capacity, shared bandwidth, satellite network, and that would be relatively efficient and automated from a network management standpoint.